Digital coursework

-Coventry University                                                                                                                                 Faculty of Engineering and Computing

Coursework Task Sheet – be sure to keep a copy of all work submitted


Section A – To be completed by the student
Family Name(s)

 

Module No.

201CDE

Forename(s)

 

ID Number(s) (from your student card)

 

Submit via the module Moodle site by 23:55 on

11th December 2015

Time taken (hrs) (per student for group coursework)

 

 

Lecturer

Dr A Mumtaz

Hand out date:

20th November

Module Code and Title

201CDE Analogue and Digital Electronics 2

No late work accepted. Extensions allowed only in extenuating circumstances. It is important that the work submitted is an individual effort. The penalties for plagiarism are severe. Full details on Faculty coursework policy and procedures are available at https://students.coventry.ac.uk/EC/Pages/Procedures.aspx
Assignment No. / Title

Digital Coursework

Estimated Time (hrs)

15

Assignment type:

Individual

% of Module Mark

25%

Section B – To be completed by the assessor
Marks breakdown Max Awarded
Sequential design 25  
VHDL model and simulation 25  
Assessor’s signature

 

Total

50

Total
Internal moderators’ signature

 

This section may be used for feedback or other information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Learning outcomes assessed

1.     Analyse and design synchronous sequential systems.

2.     Model digital systems for simulation and synthesis using an HDL.

Assessment criteria

The work will be assessed against an approved marking scheme. A perfectly correct technical solution presented to high professional standards with commentary and insights including detailed references and demonstrating additional research can expect to be awarded >80%. Marks will be lost for errors, missing sections, poor presentation and lack of detail in analysis and commentary.

 

This coursework involves the design and simulation of a synchronous sequential counter using a traditional approach employing small scale logic components and a modern approach using behavioural modelling with VHDL. The design specification for each student is unique and based on their student ID number.

Submit through Moodle as a pdf document naming the file name with your student identification number (eg 1234567.pdf).

Specification

List the members of your team here:

Name Student Identification Number
   
   

 

Choose the student identification number of one of the team and write down the number below. An example is shown so that you know what to expect.

Example

1 4 2 7 5 1 4

 

Actual SID

             

 

The digits in your ID number, in the left to right order are used to specify the sequential output that a synchronous counter will produce in response to applied clock pulses. Assume that the ID digits are represented in a conventional 4-bit BCD code. The behaviour required of the counter is that it produces a 4-bit digital output that represents the BCD value of the successive digits of your ID number in the left to right sequence above. Once the right hand digit is output the counter will go back to the first and the sequence repeats. Note the digits represent the outputs of the counter and not its state variables. If your ID number is even you must implement the counter with JK flip-flops, if it is odd you should use D-type flip-flops.

 

  1. Traditional design

Draw a state diagram to represent the behaviour of the counter you are required to design. It is suggested you employ the letters of the alphabet to refer to each state and keep the outputs as decimal numbers at this stage.

Insert state diagram here. (2 marks)

 

Convert the state diagram into its associated state table.

Insert state table here. (2 marks)

 

Assume that a simple binary state variable allocation can be made and that any unused states can be treated as don’t cares. Draw the corresponding transition table for the counter including flip-flop inputs and BCD outputs for your designated storage device.

Insert transition table here. (4 marks)

 

Using excitation maps determine the next state logic functions that can be used to drive your flip-flop inputs.

Insert excitation maps clearly showing groups and logic functions here. (6 marks)

 

Also draw Karnaugh maps to deduce minimal logic functions for the 4 output functions that are required to give the BCD output codes. Note that depending on your ID number not all outputs will be significant in all cases.

Insert the output function maps and logic equations here. (5 marks)

 

Enter the associated schematic circuit diagram here. (6 marks)

 

 

  1. VHDL Design

For exactly the same counter specification in part 1, write a VHDL entity and architecture that will model the required sequential behaviour. The VHDL code should be entered in a VHDL tool such as Simili or Xilinx Vivado to confirm that it compiles without errors.

Insert your VHDL model design with proof of compilation here. (9 marks)

 

Also write a test bench that will enable the correct function of the counter model to be simulated. Again include proof that it compiles without errors on your design tool.

Insert your VHDL test bench here. (8 marks)

 

Finally include output from the simulator that proves your design simulates correctly. Briefly explain why you consider the result gives this proof. Insert simulation results and commentary here.

(8 marks)

 

The Faculty Policy on Assessed Coursework applies to this coursework. You are advised to read the guidelines available on the general Faculty CU online web site.

Keep a safe copy of all coursework submitted for reference.

 

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